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BEGIN:VEVENT
SUMMARY:Logic Synthesis and Verification
DTSTART;TZID=Europe/Madrid:20110622T110000
DTEND;TZID=Europe/Madrid:20110701T110000
DTSTAMP:20260417T114206Z
UID:61bc3438d17ed51b53aa2541dd43b5b9@peter6.upc.edu:11901
CATEGORIES:Course
CREATED:20110602T070800Z
LAST-MODIFIED:20110609T132000Z
LOCATION:Room S215 (floor -2)\, Building Omega\, Campus Nord\, UPC
URL:https://computing.phd.upc.edu/en/events/logic-synthesis-and-verificati
 on-1
END:VEVENT
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TZID:Europe/Madrid
X-LIC-LOCATION:Europe/Madrid
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DTSTART:20110327T030000
TZNAME:CEST
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
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